一种新的低功耗BIST测试生成器设计

A New Design of Low Power BIST TPG

文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低。由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值。

This paper considers a new BIST TPG that can highly reduce the power consumption during test without losing stuck-at fault coverage .By adding simple control logic on original LFSR ,both the outputs and the clock of the LFSR are modified ,and pseu-SIC(single input change) test set can be gained ,which highly reduce the average power consumption of the CUT. This new design has better application value because of its less area expense.