MPEG-2视频系统纠错编解码的FPGA实现

FPGA Implementation of Error Correction Code in MPEG-2 System

针对MPEG - 2传输流 ,提出了在通信信道传输时结合交织的纠错编解码方案 ,并完成硬件实现。纠错编码部分包括RS码、卷积交织和增信删余卷积码 ,采用硬件描述语言VHDL作设计输入 ,使用现场可编程门阵列FPGA实现。纠错解码部分主要采用专用解码芯片实现。结合了纠错技术的MPEG- 2视频系统使传输误码率从 10 - 2 ～ 10 - 3降低到 10 - 7～ 10 - 8,该系统已经应用于实时监控中 ,性能良好。

A FEC scheme combined with interleaving and its hard wa re implementation aiming at the transmission of MPEG-2 Transport Stream in commu nication channel are proposed. The FEC encoding part including RS coding, convol utional interleaver and punctured convolutional coding,is designed with VHDL and implemented with FPGA,and the FEC decoding part implemented with dedicated IC. The MPEG-2 system combined with FEC has reduced BER from 10 -2～10 -3 to 10 -7～10 -8,and been used in real-time monitor,and got good res ult.