32位时延无关异步流水线乘法器设计

A 32-bit Delay-Insensitive Asynchronous Pipelined Multiplier

提出采用Heaviside函数建立可精确描述门限门行为的数学模型,该数学模型可描述门限门的置位、复位行为.针对异步单轨逻辑健壮性差的缺点,基于零协议逻辑(NullConventionLogic)设计了双轨逻辑的时延无关32位异步流水线乘法器.乘法器基于改进的Booth编码和Wallace树.该乘法器与采取同样结构的同步乘法器的仿真结果表明,前者的性能提高了近4倍.

Heaviside function was proposed to create a precise arithmetic model of the threshold gate. The model can describe both the set and reset behavior of the threshold gate. Asynchronous circuits based on the single-rail logic have poor stability, so a dual-rail delay-insensitive 32-bit pipelined multiplier was designed by Null Convention Logic (NCL). The multiplier is based on modified Booth encoding and Wallace tree. Both the multiplier and its synchronous counterpart were tested. The performance of the asynchronous multiplier outdoes the synchronous one by several times.