摘要
该文分析了在总线数小于min(存贮器模块数目,处理机数目)的情况下,多总线多处理机系统的有效存贮器带宽性能。提出有效存贮器带宽的概率模型,对结果进行分析、仿真与其它模型结果进行比较。
This paper studies the performance of the effectivememory bandwidth of multiple bus multiprocessor systems when thenumber of buses is less than min (the number of memory modules,the number of processors). The probabilistic model is proposed. Theresults predicted by this model are analyzed, simulated, and com-pared with the other model where there exists.
出处
《南京理工大学学报》
EI
CAS
CSCD
1993年第6期71-75,共5页
Journal of Nanjing University of Science and Technology
关键词
性能鉴定
多处理机
仿真
存贮器
performance tests
multiprocessor systems
simulation
effective memory
bandwidth
