摘要
提出了一种测量闪速存储器存储单元浮栅电压耦合率的方法.研究了采用负栅源边擦除的存储单元出现的退化现象,认为在擦除过程中源极附近的空穴注入产生界面态和氧化层陷阱,由该界面态和氧化层陷阱形成的应力导致漏电流是引起这种器件退化的最主要的原因.在此基础上描述了应力导致的漏电流退化的3种可能的导电机制,并且分别测量出应力导致的漏电流中瞬态和稳态电流的大小.研究表明,在读操作应力下,可靠性问题主要是由电子通过氧化层隧穿引起的.
A method for measuring the coupling rate of the floating-gate voltage in Flash Memory cells is presented and proved to be feasible. Meanwhile, the degradation of Negative Gale source-side erased Flash Memory cells is investigated. Interface states and oxide traps were generated by hot-carrier injection near the source during this erasing process, by which the SILC generated is the major cause for device degradation, on the basis of which, three possible conduction mechanisms are described. The steady-state current and the transient one in the SILC are measured respectively. The conclusion can be drawn from this study that the reliability issue under the action of reading stress is mainly caused by electron tunneling through oxides.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2004年第6期821-824,共4页
Journal of Xidian University
基金
国家863计划VLSI重大专项资助项目(2004AA1Z1070)
国家部委预研计划资助项目(41308060305)
关键词
闪速存储器
耦合率
应力导致的漏电流
Current voltage characteristics
Electron device testing
Hot carriers
Oxides
Stress analysis