GPS接收机中采样平均技术的FPGA实现

An Averaging Method of Signal Sampling Realized with FPGA for GPS Reciever

提出了一种采样平均的处理方法 ,将每毫秒 50 0 0点的采样信号变成每毫秒 1 0 2 4点 ,并利用现场可编程门阵列 (FPGA—fieldprogrammablegatearray)实现了这种方法。利用Matlab进行的仿真和ISE(insystememulator)综合结果表明这种方法不会影响信噪比 ,而且简化了接收机的相关处理器 ,节省了FPGA资源 ,降低了接收机成本 ,提高了处理速度 。

A new method is introduced to downsample the incoming signal from a sampling rate of 5000 samples/ms to 1024 samples/ms,which has been realized with FPGA(field programmable gate array).The simulation results obtained with Matlab and the synthesis results obtained from ISE(insystem emulator)show that this method would not degrade the SNR;besides,it can simplify the correlation processor of GPS receiver,save the FPGA source,reduce the price of the receiver,raise the processing speed and speed up the designing process.