摘要
设计了一种基于1stSilicon0.25μmCMOS工艺的全集成SARA/D转换器。详细介绍了SARA/D转换器的基本原理、电路结构和仿真结果。该SARA/D转换器采用全差分结构,系统时钟频率为2MHz,精度12位,采样速率125kb/s,输入电压范围0～2.5V。在3.3V供电电压下,功耗为0.3mW,芯片有效面积为745μm×2000μm。
A fully integrated CMOS SAR A/D converter based on 1^(st) Silicon 0.25 μm CMOS process for PDA system is designed. The principle and architecture of the SAR A/D converter is described, and simulation results are also provided. Based on a fully differential structure, the device has a system clock frequency of 2 MHz for a supply voltage of 3.3 V with an input voltage from 0 to 2.5 V and a power consumption of 0.3 mW. With a chip size of 745 μm × 2000 μm,the A/D converter has achieved a sampling rate of 125 kb/s and a 12-bit resolution.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第6期694-697,共4页
Microelectronics
基金
天津市科技攻关重点项目资助(033187111)
