一种具有改进积分器结构的高阶Σ-Δ调制器

A Higher-Order Σ-Δ Modulator with Improved Integrator Structure

设计了一个五阶单回路Σ-Δ调制器,最高输入信号频率22kHz。通过改进积分器的结构,显著减小了开关电荷注入效应引起的调制器的谐波失真。整个电路采用0.6μmCMOS工艺设计。仿真显示,当采样频率为6MHz时,调制器的SNDR达到123dB,SNR超过125dB,满足18位A/D转换器的精度要求。

A fifth-order single loop Σ-Δ modulator capable of converting input signals up to 22 kHz is presented. An improved structure of switched-capacitor integrator is used to reduce the harmonic distortion induced by charge-injection effect. The circuit is designed in a 0.6 μm CMOS technology. Results from simulation show that an SNDR of 123 dB and an SNR over 125 dB have been achieved for the circuit at a sampling frequency of 6 MHz, satisfying the demand of an 18-bit analog-to-digital converter.