14位1.5625MHz的ΣΔA/D中的降采样低通滤波器的设计

Design of the Decimation Low Pass Filter Used in a 14-b 1.5625 MHz Sigma-Delta A/D Converter

介绍了带宽为 70 0kHz ,14 bitΣΔ模数转换器中的降采样低通滤波器的设计。在整个滤波器的设计中 ,从结构上和硬件实现上入手 ,对电路结构进行优化 ,减小电路实现的复杂性 ,从而降低功耗和面积。在此基础上 ,完成了电路设计 ,用 0 .6 μmCMOS工艺综合实现 ,仿真结果显示 ,性能满足设计指标。

The design of a decimation low pass filter used in a 14-b 1.5625 MHz Sigma-Delta A/D converter is presented in this paper. In the design of this filter, at all levels from architecture to hardware implementation, techniques are applied to optimize the circuit structure and reduce the circuit complexity in order to minimize the power dissipation and area. Finally, the circuit is synthesized targeted to 0.6 μm CMOS technology. The simulation result proves that its performance meets the design specification.