一种快速以太网卡芯片时钟恢复电路

A Clock Recovery Circuit for Fast Ethernet Application

提出了一种快速以太网卡芯片时钟恢复电路的设计 ,包括体系结构、用于 10 0BASE TX的改进MuellerMuller算法、用于 10 0BASE FX的鉴相器以及产生多相时钟的电荷泵锁相环。该时钟产生电路经过TSMC 0 .35 μm1P5MCMOS工艺验证 ,工作电压为 3.3V。实验结果表明该时钟恢复电路能够满足以太网卡芯片的要求。

This thesis presents a circuit architecture to realize clock recovery for fast Ethernet application, including system architecture, modified Mueller Muller algorithm for 100BASE-TX, phase detector for 100BASE-FX and multiple output charge pump PLL. The clock generator circuit with 3.3 V operation voltage has been verified by TSMC 0.35 μm 1P5M CMOS process. The results show that this clock recovery circuit can exactly extract the timing information. It has advantages over other ones for simplicity and easy implementation.