摘要
本文从简化触发器内部锁存器结构以降低功耗的要求出发,提出了一种新型的半静态D触发器设计。PSPICE模拟表明,新设计逻辑功能正确。与以往一些设计相比,新设计在功耗和速度上获得显著改进。
To reduce power dissipation of D flip-flops by means of simplifying its configuration, a new design of semi-static D flip-flop is proposed. PSPICE simulation shows that the proposed flip-flop has ideal logic function. Compared with traditional flip-flops, new design can provide great improvement in working speed and power dissipation.
出处
《电路与系统学报》
CSCD
2004年第6期26-28,共3页
Journal of Circuits and Systems
基金
国家自然科学基金资助项目(60273093)