SOC可测试性设计与测试技术

Design-for-Testability and Test Technologies for System-on-a-Chip

超深亚微米工艺和基于芯核的设计给芯片系统(system-on-a-chip,SOC)测试带来了新的问题.对SOC可测试性设计与测试技术的国际研究现状及进展进行了广泛而深入的综述.从芯核级综述了数字逻辑、模拟电路、存储器、处理器4类芯核的可测试性设计与测试技术,从系统级综述了测试激励、测试响应和测试访问机制等SOC测试资源的设计以及压缩／解压缩与测试调度等测试资源划分、优化技术,并介绍了2个标准化组织开展的SOC测试标准工作.最后,展望了SOC测试未来的发展方向.

A comprehensive survey of the up-to-date design-for-testability (DFT) methods and testing technologies for system-on-a-chip (SOC) is presented. The techniques of DFT and testing for embedded cores of digital, analog/mixed-signal, memory and processor are introduced respectively. Among these techniques, some advanced scan and built-in-self-test schemes to provide at-speed test capability or to reduce test application time, test power consumption and test data volume are emphasized. The DFT and testing techniques for SOC at system level are also surveyed. Since test resources are very important to cope with new issues of testing SOC, design, partitioning and optimization of test resources are described in detail. In an SOC, on-chip test resources generally include test access mechanism, test wrapper, and test source and sink. For test source and sink, test resource partitioning approaches based on test stimuli compression/ decompression and test response compaction are overviewed. For test access mechanism and test wrapper, test resource optimization techniques of test scheduling based on heurist algorithms are presented. The SOC test standardization by two organizations is introduced. Finally, some future directions in DFT and test technologies for SOC are indicated, and an extensive bibliography is also provided.