流水线纠错纠删RS译码器的设计和实现

The design of pipelined errors-and-erasures correcting Reed-Solomon decoders and its implementation

在传统纠错RS译码器设计的基础上 ,采用分解的无逆B M (iBM )算法和三级流水线的电路结构 ,实现流水线纠错纠删RS译码器的设计 .该设计的特点是 :控制时序简单 ;电路实现简洁 ;纠错能力强 ,可纠错和纠删 ;译码速度高 ,数据吞吐率达到 1byte/时钟 ;采用VerilogHDL实现 ,可重复利用 .该设计应用于DVD数据纠错的实现中 ,达到系统的性能要求 .

Based on the conventional errors correcting Reed Solomon(RS) decoder, an pipelined errors and erasures correcting RS decoder was presented by a novel modified decomposed inversionless Berlekamp Massey(B M) algorithm and three stage pipeline architecture. The RS decoder was characterized by the followings: easy timing control, direct circuit implementation, errors and erasures correcting, high speed with a rate of 1?byte per clock cycle, Verilog HDL implementation suitable reused in other relative VLSI design. The design was for DVD applications, and satisfied the system performance requirement.