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Low power DCVSL circuits employing AC power supply 被引量：3

Low power DCVSL circuits employing AC power supply
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摘要 In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations. In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.
作者 吴训威 杭国强 Massoud Pedram
机构地区 Institute of Circuits and Systems
出处 《Science in China(Series F)》 2002年第3期232-240,共9页 中国科学（F辑英文版）
基金 This work was supported in part by the National Natural Science Foundation of China ( Grant No.69973039) and National Science Foundation of USA (Grant No. 9988441) .
关键词 VLSI design low power technique AC power clocked DCVSL circuit. VLSI design, low power technique, AC power, clocked DCVSL circuit.
分类号 TM46 [电气工程—电器]
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共引文献28

同被引文献30

  • 1谢修祥,王广生.异步多时钟系统的同步设计技术[J].电子工程师,2005,31(5):33-37. 被引量：15
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  • 4MOON Y, JEONG D K. An efficient charge recovery logic circuit[J]. IEEE Journal of Solid-State Circuits, 1996, SC-31(4): 514-522.
  • 5OKLOBDZIJA V G, MAKSIMOVIC D, LIN F. Pass-transistor adiabatic logic using single-clock supply[J]. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 1997, 44(10): 842-846.
  • 6LIU F, LAU K T. Pass-transistor adiabatic logic with NMOS pull-down configuration[J]. Electronics Letters, 1998, 34(8):739-741.
  • 7NG K W, LAU K T. Improved PAL-2N logic with complementary pass-transistor logic evaluation tree[J]. Microelectronics Journal, 2000, 31(1):55-59.
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  • 9NG K W, LAU K T. Low power flip-flop design based on PAL-2N structure[J]. Microelectronics Journal,2000, 31(2): 113-116.
  • 10Blotti A,Saletti R.Ultralow-power adiabatic circuit semi-custom design[J].IEEE Tran.on VLSI Systems,2004,12(11):1248-1253.

引证文献3

二级引证文献5

Science in China(Series F)
2002年 第3期

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