千兆以太网CRC的算法与VLSI设计与实现

VLSI Design and Implementation of CRC in Ethernet

介绍了CRC的数学原理及具体在以太网中的算法与VLSI实现方式。以CRC-8为例,介绍了串行结构实现及并行输入的推导,并给出了Verilog HDL编程及相关技术。串行移位结构的数据吞吐量无法满足千兆以太网1Gbps的要求,设计了一种8bits的并行VLSI结构,用0.25μm CMOS单元库综合后得出数据吞吐量达到2Gbps,完全满足要求。

This paper describes the CRC mathematical principle and the concrete design and implementation in Ethernet. Taking the CRC-8 as an example, it introduces the serial shift structure and then deduces the parallel data input structure. Then it introduces the verilog program and relevant techniques. The data throughput of serial shift structure can't meet the demand of gigabit Ethernet(1 Gbps). The paper designs a VLSI structure of 8-bits parallel data input whose data throughput can be 2Gbps after DC synthesis and of course meets the demand.