一种高效的JPEG2000位平面编码器设计

Design of High Efficient JPEG2000 Bit-Plane Encoder

针对JPEG2000 芯片实现时的硬件复杂性和编码效率低的问题,通过分析编码所需状态变量的产生机制,得到了一种最高有效位(MSB)检测电路,它能使状态变量实时产生.同时,在 3 个通道编码时引入列快速扫描电路,它在清除通道编码中设计了游程编码和0编码的流水实现电路,最后得到了位平面编码器 0冗余时钟设计.将此方法用于实现三通道并行的位平面编码器时,相对于单通道的跳点跳列,其运算速度可提高2倍,逻辑电路节约50%,而对于64×64像素的码块,存储器节约20 kb.

Focusing on the problem that the hardware complexity and low encoding efficiency exist in JPEG2000 chip implementation, a most significant bit (MSB) detection circuit was obtained through analyzing of generation mechanism of state variables, which can generate state variables in real time when the data is accessed from the code block memory. Meanwhile a column scan circuit was put into the three pass encoder, and a pipeline sequence generation circuit for run length coding and zero coding was designed in the clean-up pass coding. Finally, a bit-plane encoder with zero redundancy clock was implemented. When the method is used for implementing three-pass parallel bit-plane encoding, the operation speed is increased two times compared with the encoder realized by pixel skip and GOCS (group of column skip) the logic resources is saved about 50%, and the memory is saved about 20 kb for the size of the code block 64×64.