摘要
在应用测控系统的设计中,为了进行准确的测量和控制,必须消除被测信号中的噪音和干扰。在传统的应用系统中,滤波部分可看作一个二端口网络,需占用较多的软硬件资源。本文用硬件描述语言(VHDL)编程,通过复杂可编程逻辑器件(CPLD)来实现数字滤波。该方案能适应多种需要的信号滤波,具有可移植性,并在实际应用中得到验证,能有效地滤除干扰信号。
Filtering and anti-jamming were an important problem that must be considered in every intelligent instrument system. In the traditional application system, a number of resources of software and hardware were occupied by filtration. With the popularization of the Complex Programmable Logic Device (CPLD), it was a method with high efficiency and credibility that the filter was realized by CPLD. This paper introduced the method of filter and anti-jamming utilized CPLD ,which was programmed by MAX+PLUSⅡ.
出处
《国外电子测量技术》
2005年第1期30-31,共2页
Foreign Electronic Measurement Technology