引信体目标视频回波模拟器SDRAM控制器的FPGA设计

FPGA Design of SDRAM Controller for Wireless Fusee Body-Target Video Frequency Echo Simulator

针对引信体目标视频回波模拟器中高速大数据量传输、下载和存储的需要,提出了用现 场可编程门阵列(FPGA)设计SDRAM控制器的方案和方法。该控制器与常规SDRAM控制器不 同,它以长度120个字为一组进行突发(Burst)的读写,内部操作也不同于整页的读、写操作机制,而 是采用了内部计数器到固定周期数给出截断(Terminate)和预充电(Precharge)命令的一种操作方 式。经验证,该控制器在片工作频率可达100 MHz,满足了引信体目标视频回波模拟系统对引信与 目标的相对运动参数预先产生回波数据的高速大数据量下载的要求。

A SDRAM controller for wireless fusee body-target video frequency echo simulator is designed based on FPGA. In this SDRAM controller, the burst length is 120 words, and its internal operation is also different from the full page burst,which adopts inner logic to send out terminate and precharge commands at fixed period- It has been demonstrated that the controller can achieve an operating frequency up to 100 MHz, satisfying the demand of the system for high-speed download of large volume of data.