基于FPGA的高速图像预处理系统设计

A FPGA-Base High-Speed Image Pre-Processing System Design

介绍了一种用单片FPGA实现的实时、多任务、高速图像处理系统。该系统承担着提高信噪比、压缩数据量、Stokes参数观测和仪器及观测模式控制等任务。针对一个星载系统,采用了核心逻辑片内冗余、设计了相应的冗余管理线路等可靠性设计技术,采用了放置片内测试和校验模块等可测性设计技术,使系统工作时钟达40 MHz,图像处理速率达100 Mbps。

A single-chip Field Programmable Gate Array(FPGA) Image pre-processing system is introduced. This system is used to complete a series of real-time, multi-task and high-speed image processing tasks, including improving image signal-to-noise ratios, compressing data volume, stokes parameters observation, instrument control and observation mode control, etc. As an on-board system, the reliability of the system is very important, so the core logic modules are redundant. Moreover, Built-in Testing(BIT) module and EDAC(Error Detection And Correction) module are also placed in FPGA. System clock was 40 MHz, and its images processing ratio attained to 100 MHz.