MPEG-4视频变长码并行解码器硬件实现

Hardware Implementation of Parallel MPEG-4 Video Variable Length Decoder

提出了一个MPEG 4变长码并行解码器的硬件设计.采用桶形移位器、基于PLA的并行解码算法等方法使得每个时钟周期解一个变长码码字.通过将码表改造、分割长码表为几个短码表并行查表、使用流水线技术等措施减少关键路径的延时以提高工作频率,保证了MPEG 4ASP@L5格式码流的实时解码.

This paper presents a parallel design of MPEG-4 Variable Length Decoder. The design uses barrel shifter and PLA-based parallel algorithm so that one variable length code can be decoded in every clock cycle. Some special approaches, such as pipelining, reconstructing variable length code tables and partitioning a long look-up table into several shorter ones, which facilitates parallelity, are introduced. These can reduce delays on critical path, thus raising working frequency. Real-time MPEG-4 ASP@L5 decoding is ensured by the foresaid methods.