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光纤通道交换机MAC帧处理的设计与实现 被引量:1

Design and Implementation of MAC Frame Processing on Fibre Channel Switch
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摘要 介绍了1Gb/s速率8×8光纤通道交换机的体系结构,并详细论述了光纤通道交换机帧处理流程和基于FPGA的帧处理的设计与实现。经过时序仿真,验证了帧处理设计的正确性。该设计与实现对完成光纤通道交换机的研制具有典型意义。 This paper discusses a system architecture of Fibre Channel(FC) switch,which has 1Gb/s serial data rates and 8x8 synchronous serial crosspoint switch. The design and implementation of frame processing are introduced in details. And the design is proved by timing simulation. The results announce the importance of research on Fibre Channel switch.
出处 《光通信技术》 CSCD 北大核心 2005年第1期58-61,共4页 Optical Communication Technology
关键词 光纤通道交换机 CRC MAC FPGA fibre channel switch cyclic redundancy che- ck(CRC) MAC FPGA
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参考文献3

  • 1American National Standards Institute. Fibre Channel Framing and Signaling-2 ( FC-FS-2 ),Rev0.01 ,July 3,2003.
  • 2American National Standards Institute. Fibre Channel Physical and Signaling Interface (FC-PH),Rev4.3 ,June 1,1994.
  • 3Sait S M,Hasan W. Hardware Design and VLSI Implementation of a Byte-wise CRC Generator Chip. IEEE Transactions on consumer Electronits, 1995,41 (2): 195 - 200.

同被引文献8

  • 1胡学良,张春,王志华.JTAG技术的发展和应用综述[J].微电子学,2005,35(6):624-630. 被引量:16
  • 2Michael D Ciletti.Verilog HDL高级数字设计[M].张雅绮,李锵,译.北京:电子工业出版社,2005:510-582.
  • 3Altera Corporation.器件封装规范[EB/OL].(2006-02-21) http://www.altera.com.cn/support/devices/packaging/specifications/pkg-pin/spe-index.html.
  • 4Bhasker J.Verilog HDL硬件描述语言[M].徐振林,译.北京:机械工业出版社,2002:115-155.
  • 5Altera Corporation.Signal TapⅡembedded logic analyzer[EB/OL].(2004-06-24)http://www.altera.com.cn/products/ software/pld/design/verification/signaltap2/sig-index.html.
  • 6Altera Corporation.Design debugging using the Signal Tap Ⅱ embedded logic analyzer,QuartusⅡ5.1 handbook,volume 3[EB/OL].(2005-12-13) http://www.altera.com.cn/literature/ hb/qts/qts_qii53009.pdf.
  • 7王金明.数字系统设计与Verilog HDL[M].北京:电子工业出版社,2006:47-50.
  • 8匡迎春.一种数字式仪表的量程自动转换装置的研制[J].湖南农业大学学报(自然科学版),2002,28(6):519-521. 被引量:4

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