摘要
采用上华0 6μmDPDMCMOS工艺,设计实现了一种基于片上系统应用的低功耗、高增益Rail to Rail运算放大器IP核.基于BSIM3V3Spice模型,采用Hspice对整个电路进行仿真,在5V的单电源电压工作条件下,直流开环增益达到107 8dB,相位裕度为62 4°,单位增益带宽为4 3MHz,功耗只有0 34mW.
Based on SOC application, a Rail-to-Rail operational amplifier IP core with a low-power and a high gain is presented. The operational amplifier will be realized in the CSMC 0.6μm DPDM CMOS process. The whole circuit is simulated with the BSIM3V3 Spice model in Hspice. With a single power supply of 5V in simulation, it is shown that the Rail-to-Rail operational amplifier has an open loop gan of 107.8dB, a phase margin of 62.4 degrees and a unit gain bandwidth of 4.3MHz, with the static power dissipation being only 0.34mW.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2005年第1期112-115,共4页
Journal of Xidian University
基金
国家部委预研基金资助项目(51408010601DZ01)