摘要
介绍了锁相环芯片NE5 6 4的结构和性能 ,根据图像采集的要求设计了倍频锁相电路 ,能够产生高频锁相时钟。采样时钟可以跟踪行频的变化实现非标准视频图像的稳定采集。在CPLD内部设计分频器可以根据采集的需要灵活地改变时钟的分频倍数 ,实现不同格式的图像采集。
High frequency clock phase-locked with synchronous sig na ls is necessary for nonstandard Video signal acquisition system. The configurati on and capability of phase-lock loop chip NE564 are introduced in this paper. Fr equency-multiplication phase lock circuit is designed to generate high frequency clock. Nonstandard video signal is captured stably with the clock. The frequenc y divider is designed in CPLD. Various format of image collection could be obtai ned with the change of parameters in software.
出处
《长春理工大学学报（自然科学版）》
2004年第4期98-100,共3页
Journal of Changchun University of Science and Technology(Natural Science Edition)
基金
中科院长春光机所青年创新基金 (Q0 3T0 3Z)
关键词
图像采集
倍频锁相
同步
video signal acquisition
Frequency-multiplication phas e lock
synchronization
