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Formal Verification under Unknown Constraints 被引量:1

Formal Verification under Unknown Constraints
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摘要 We present a formal method of verifying designs with unknown constraints (e.g., black boxes) using Boolean satisfiability (SAT). This method is based on a new encoding scheme of unknown constraints, and solves the corresponding conjunctive normal form (CNF) formulas.Furthermore,this method can avoid the potential memory explosion, which the binary decision diagram (BDD) based techniques maybe suffer from, thus it has the capacity of verifying large designs. Experimental results demonstrate the efficiency and feasibility of the proposed method. We present a formal method of verifying designs with unknown constraints (e.g., black boxes) using Boolean satisfiability (SAT). This method is based on a new encoding scheme of unknown constraints, and solves the corresponding conjunctive normal form (CNF) formulas.Furthermore,this method can avoid the potential memory explosion, which the binary decision diagram (BDD) based techniques maybe suffer from, thus it has the capacity of verifying large designs. Experimental results demonstrate the efficiency and feasibility of the proposed method.
出处 《Wuhan University Journal of Natural Sciences》 EI CAS 2005年第1期43-46,共4页 武汉大学学报(自然科学英文版)
基金 Supported by the National Natural Science Foun dation of China (90207002),the Science and Technology Project ofBeijing (H020120120130),and in part by the Zhejiang ProvincialNatural Science Foundation of China (M603097).
关键词 formal verification unknown constraints black box Boolean satisfiability Boolean comparison formal verification unknown constraints black box Boolean satisfiability Boolean comparison
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  • 1Kern C,Greenstreet M.Formal Verification in Hardware Design: A Survey[].ACM Transactions on Design Automation of E Systems.1999
  • 2Larrabee T.Test Pattern Generation Using Boolean Satisfiability[].IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems.1992

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