高速CMOS/SOI电路输入保护网络的优化设计

Optimum Design of Input Protection Networks for CMOS/SOI Circuits

报道CMOS/SOI集成电路中输入保护网络的优化设计.从网络内部参数、总体设计的理论分析以及失效测试等方面讨论了各种因素对静电失效的影响,并在此基础上成功地研制了抗静电能力超过2000V、电路平均单级门延迟小于2.7ns的输入保护网络.

Optimum input protection network for high speed CMOS/SOI circuits is reported in this paper, This paper describes the results of a program undertaken to develop a protection network and the application in 300-gate CMOS / SOI gate array. The optimum network is capable of protecting circuits from static discharge in excess of 2000V and the propagation delay of per-gate is only 2.7ns.