用于亚微米CMOS的自对准硅化钛工艺

Self-aligned Titanium Silicidc Tcchnolog for Submicron CMOS

本文研究了用溅射钛和快速退火法与硅反应形成硅化钛的工艺,二氧化硅侧墙轻掺杂漏结构的CMOS工艺加上该工艺后,器件的阈值电压、源漏击穿电压没有明显变化,但使CMOS的栅电阻降低一个数量级,源漏串联电阻为原来的1/4。肌此工艺已研制成功3μm NMOS 12位乘法器,比没有硅化物的器件速度提高一倍。

This paper presents a sclf-aligned Titanium silicidc (SALICIDE) Technolog. After forming SiO side wall LDD, titanium was sputtered. Then two steps rapid thermal annealing was used. Thus the sheet resistance of polysili(?)on gate region de(?)reases by one order of magnitut, the sheet resictance of active region decrease by four times. Using this technology, thershold voltage and source drain br(?)akdwon voltage was not changed. LDD SALICIDE 3μm NMOS multiplirs were fabricated, Multiplication speed of them is 130ns while conventional one is 250ns.