用Verilog硬件描述语言实现Viterbi译码

Implementation of Viterbi Decoding With Verilog HDL

介绍了Viterbi译码的原理,并用Verilog硬件描述语言设计实现了Viterbi译码.实验表明,用这种硬件实现的Viterbi译码器译码速率高达40M,远比用软件实现Viterbi译码快.

This paper presents principles of Viterbi decoding, and deals with the hardware implementation based on the Verilog HDL. The experimental results show the rate of Viterbi decoding device based on the hardware is up to 40M, far much faster than the software implementation.