期刊文献+

一种抗总剂量辐照的NMOSFETs 被引量:1

Total Dose Radiation Hard NMOSFETs
下载PDF
导出
摘要 在商用 SIMOX衬底上制备了抗辐照 NMOSFETs,使用的主要技术手段有 :氮化 H2 -O2 合成栅介质加固正栅 ;增加体区掺杂 ,以提高背栅阈值电压 ;采用 C型体接触结构 ,消除边缘寄生晶体管。结果表明 ,在经受 1× 1 0 6 rad( Si)的辐照后 。 Total dose radiation hard NMOSFETs were fabricated on SIMOX substrate. The used technologies are N_2O annealed H_2-O_2 grown dielectric for the front gate hardness, high doping of the body region to increase the back gate threshold voltage, and a C-type body-tie structure to eliminate the lateral MOS transistor. The results show that the characteristic of the NMOSFETs did not change much after the radiation of 1×10~6 rad(Si).
出处 《电子器件》 CAS 2004年第4期578-580,共3页 Chinese Journal of Electron Devices
关键词 :SOI 总剂量辐照 氮化H2-O2合成栅介质 C型体接触 SOI total dose radiation N_2O annealed H_2-O_2 grown dielectric C-type body-tie structure
  • 相关文献

参考文献8

  • 1Liu Xinyu, Liu Yunlong, Sun Haifeng, et al. Chinese Journal of Semiconductors[J]. 2002,23:213(in Chinese).
  • 2Davis G E, Hite L R, Blake T G W, et al. IEEE Trans Nucl Sci[J]. 1985,32:4432.
  • 3Leray J L. Dupont-Nivet E, Pere J L, et al. IEEE Trans Nucl Sci[J]. 1990,37:2013.
  • 4Lo G Q, Joshi A B, Kwong D L. IEEE Trans Electron Devices[J]. 1993,40:1565.
  • 5Mao B Y, Chen C E, Pollack G, et al. IEEE Trans Nucl Sci[J]. 1987,NS-34:1692.
  • 6Liu S T, Jenkins W C and Hughes H L. IEEE Trans Nuclear Sci[J]. 1998,45(6):2442-2449.
  • 7Leray J L, Dupont-Nivet E, Musseau O, et al. IEEE Trans Nucl Sci[J]. 1988,35:1355.
  • 8Liu X Y, Liu Y L, Sun H F, et al. Chinese Journal of Semiconductors[J]. 2001,22(12):1596-1599(in Chinese).

同被引文献14

  • 1沈鸣杰,戴忠东,俞军.一种新型的抗单粒子翻转的D触发器[J].复旦学报(自然科学版),2006,45(4):475-479. 被引量:5
  • 2赵金薇,沈鸣杰,程君侠.改进型抗单粒子效应D触发器[J].半导体技术,2007,32(1):26-28. 被引量:4
  • 3郭天雷,韩郑生,海潮和,周小茵,李多力,赵立新.PDSOI静态随机存储器的总剂量辐照加固[J].电子器件,2007,30(3):794-798. 被引量:4
  • 4Maru A,Shindou H, Ebihara T, et al. DICE-Based Flip-Flop with SET Pulse Discriminator on a 90 nm Bulk CMOS Process [ J ]. IEEE Trans on Nucl Sci ,2010,57 (6) :3602-3608.
  • 5Baze M P, Buchner S P. Attenuation of Single Event Induced Pluses in CMOS Combinational Logic [ J ]. IEEE Trans on Nucl Sci, 1997,44 (6) :2217-2223.
  • 6Ya V ,Stenin I,Cherkasuv G,et ',:d. Memnt.'y-Cell Layout as a Factor in the Single-Event-Upset Susceptibility of Submicron DICE CMOS SRAM [ J ]. Russian Micrnelectnmics, 2011,40 ( 3 ) : 170-175.
  • 7Tsai C H, Wu M H, Chang C F. Quasi-Planar Bulk CMOS Technulogy for Impn~ved SRAM Scalability [ J ]. Solid-StateElectronics,2011,65 (184) :3551-3561.
  • 8Sehwank J R, Dodd. Total Ionizing Dose and Single Event Effects Hardness Assurance Qualification Issues for Microelectronics [ J ]. IEEE Trans on Nucl Sci,2008,55(4) :.
  • 9Bhuva B L, Black J D, Massengill L W. RHBD Techniques for Mitigating Effects of Single-Event Hits Using Guard Gates [ J ]. IEEE Trans on N ucl Sci,2005,52 ( 6 ) : 2531-2535.
  • 10Favrat P. High-Efficiency CMOS Voltage Doubler [ J ]. IEEE .1 of Solid-State Circuits, 1998,33 ( 3 ) :410-416.

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部