一种改进的SRAM并行BIST电路设计

Improved parallel BIST method for SRAM

对系统嵌入式存储器进行测试是非常重要的,内建自测试(built inself test,BIST)方法是系统工作期间测试存储器的有效方法。基于存储器透明(Transparent)测试的TRSMarch算法,提出了一种改进的SRAM并行透明测试BIST接口电路。该电路适应不同大小的存储器,执行测试并响应测试中断,同时由于采用边界扫描单元,可以通过边界扫描结构(JTAG)对存储器进行有选择的测试。给出了相应BIST控制器的电路实现及其仿真结果。测试电路能实现TRSMarch算法,具有故障覆盖率高、硬件开销小的特点。

It is important to test embedded memory during system working, and built-in self-test (BIST) is an efficient method for embedded memory test. Based on TRSMarch algorithm used for SRAM transparent testing, an improved parallel transparent test interface of BIST for SRAM is presented. The interface circuit can access embedded memory arrays with various sizes, perform testing in the normal state and deal with test interrupts when the system is working. At the same time, the boundary scan cell is used in the transparent test interface, so the embedded memory under test can be selected freely in the new circuit through the JTAG test structure. The implementation of the corresponding BIST controller and its simulation results are described. The BIST circuits based on TRSMarch algorithm have some advantages such as high fault coverage and low hardware overhead.