期刊文献+

0.5μm高速BiCMOS的工艺研究 被引量:1

A Study of 0.5μm High Speed BiCMOS Technology
下载PDF
导出
摘要 报道了一套先进的0.5μm高速双层多晶硅自对准BiCMOS制作工艺。工艺中采用了先进的深槽隔离技术、选择性集电极注入(SIC)技术、使用自对准Si3N4/SiO2复合侧墙作为E-B结的隔离、用低能氟化硼取代硼注入基区形成超薄内基区。通过优化BiCMOS制作工艺,最终制作出了性能优良的高速BiCMOS器件。 An advanced high speed BiCMOS fabrication technology is presented. Some advanced technology is adopted including deep trench isolation, SIC, self-aligned Si3N4/SiO2 composite sidewall as Emitter-Base junction isolation and ultra-thin interior base formed by BF2 implantation. Finally a good device electrical performance is achieved by optimizing BiCMOS fabrication process.
出处 《微电子学与计算机》 CSCD 北大核心 2005年第1期133-135,共3页 Microelectronics & Computer
基金 国家"863"计划项目资助(2002AA1Z1560)
关键词 BICMOS工艺 SIC技术 Si3N4/SiO2复合侧墙 超簿内基区 BiCMOS, SIC, Si3N4 /SiO2 composite sidewall, Ultra-thin interior base
  • 相关文献

参考文献5

  • 1R Hadaway, et al. BiCMOS Technology for Telecommunica tions. BCTM Technical Digest, 1993:159-166.
  • 2A Watanabe, et al. Advanced BiCMOS Technology for High Si3eed VLSI. IEDM Technical Digest. 1985:841.
  • 3T Yamaguchi, et al. Process and Device Characterization for a 30-GHz fT Submicrometer Double Poly-Si Bipolar Technology Using BF2-Implanted Base with Rapid Thermal Process. IEEE Transactions on Electron Devices,1993:1484-1495.
  • 4K Inou, et al. Improvement of Narrow Emitter Bipolar Transistor Performance by In-situ Highly Doping Arsenic Polysilieon Technique. BCTM Technical Digest, 1995:93-96.
  • 5Takeo Shiba and Takashi Uchino. In Situ Phesphorus-Doped Polysilicon Emitter Technology for Very High-Speed, Small Emitter Bipolar Transistors. IEEE Transactions On Electron Devices, 1996:889.

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部