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Wishbone总线交易级建模 被引量:1

Transaction Level Modeling for Wishbone Bus Architecture
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摘要 交易级建模在系统功能建模和验证方面可以增快速度,也可以加速仿真的速度并允许在高层次抽象中研究和确认设计中可供选择的模块。针对Wishbone片上总线协议,依据SystemC中接口方法调用的基本原理和交易级建模的方法,完成了Wishbone总线中共享总线的交易级建模,结果表明SystemC适合在交易级建模系统的行为和通信,交易级建模在仿真速度方面具有优势。 Transaction level modeling allows a speed-up in modeling and verification of the functionalities of the system. It also speeds up simulation and allows exploring and validating design alternatives at the high level of abstraction. The shared bus architecture of Wishbone was finished based on the interface method call theory of SystemC and the way for transaction level modeling. The result shows that SystemC is fit to model the behavior and communication of a complex system at transaction level and TLM effectively creates an executable platform model which simulates very fast.
出处 《微电子学与计算机》 CSCD 北大核心 2005年第1期166-169,173,共5页 Microelectronics & Computer
关键词 交易级建模 片上总线 WISHBONE 寄存器传输级 Transaction level modeling,On-chip bus, Wishbone, Register transfer level
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参考文献7

  • 1Sudeep Pasricha. Transaction level modeling of SoC with SystemC 2.0.Synopsys User Group Conference (SNUG).2002.
  • 2LuKai Cai, Daniel Gajski. Transaction Level Modeling: An Overview. Proceedings of the 1^nt IEEE/ACM/IFIP international conference on Hardware/Software codesign & System systhesis. Oct, 2003.
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同被引文献4

  • 1颜伟成,陈朝阳,沈绪榜.AMBA-AHB总线接口的设计与实现[J].计算机与数字工程,2005,33(10):130-132. 被引量:6
  • 2胡建国,曾献君,陈亮,邢座程.CPU验证平台的研究与实现[J].微电子学,2006,36(1):49-51. 被引量:5
  • 3Zhang Yuhong, He Lenian, Xu Zhihan, et al. A System Verification Environment for Mixed-Signal SOC Design Based on IP Bus [C]//. 2003 5th International Conference on ASIC Proceedings(Vol. 1). Beijing, China: IEEE, 2003: 278- 281.
  • 4Pixley C, Chittor A, Meyer F, et al. Functional Verification 2003: Technology, Tools and Methodology [C]//. 2003 55th International Conference on ASIC Proceedings(Vol. 1). Beijing, China: IEEE, 2003:1 -5.

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