异步FIFO的设计与验证

Asynchronous FIFO Design and Verification

多时钟域设计的一个难题是如何避免亚稳态的产生。异步FIFO是一种不同时钟域之间传递数据的常用方法。避免亚稳态问题及空满控制信号的产生是异步FIFO设计的两个难题。传统的异步FIFO设计采用同步读写地址后比较产生空满标志的方法,面积大、工作频率低。针对这些问题,文章提出了一种新的异步FIFO设计方案,它改进格雷编码电路,提高异步FIFO的工作频率,用先比较读写地址产生空满标志,再同步到相应时钟域的方法避免使用大量的同步寄存器,减小面积空间。EDA综合及FPGA验证的结果均表明,改进后异步FIFO的性能有了显著提高。

An important problem in multi-clock domain design is how to avoid metastability.Asynchronous FIFO is a general way to communicate between different clock domains.The design of asynchronous FIFO meets with two troubles,metastability and how to generate empty and full flag correctly.Traditional FIFO design often synchronizes write/read address first,then compares them to generate empty/full signals.This design takes on too much area and can only work at a low frequency.A new method is proposed to overcome these problems.It optimizes gray code circuit to improve FIFO frequency,compares write/read address to generate full/empty flag first,then synchronizes them to cut down the quantity of synchronous registers.The results of EDA synthesis and FPGA verification both indicate that new asynchronous FIFO design has achieved a noticeable improvement.