DLL在FPGA时钟设计中的应用

Clock Designs in FPGA with DLL

在ISE集成开发环境中 ,用硬件描述语言对FPGA的内部资源DLL等直接例化 ,实现其消除时钟的相位偏差、倍频和分频的功能。时钟电路是FPGA开发板设计中的重要组成部分 ,若超过 5 0MHz就要考虑传输线和信号的完整性问题 ,利用DLL实现外部时钟的片内管理 ,可简化外部时钟电路和PCB板的设计。

The paper introduces a digital circuit dedicated to on-chip Delay-locked loop (DLL). The DLL can provide multiple phases of the source clock but also can double or divide the frequency of the source clock. These functions can be implemented with hardware language using ISE design tools. In this way the clock quality can be improved and the PCB board design becomes simple.