基于时钟控制的低功耗电路设计

Design of Low Power Circuit Based on Clock Control

在低功耗芯片设计中,设计者已广泛采用了时钟停止的方法来解决CMOS电路动态功耗问题。为实现时钟停止功能,作者分析了多种传统时钟控制电路方案,并在此基础上提出了一种新型可综合可测试的时钟控制电路。相对于传统时钟控制电路,此种方案在降低芯片功耗的同时解决了传统时钟控制电路所带来的时钟不稳定及无法进行测试的问题。

In the low-power chip design, designers have introduced stop-clock method to solve the dynamic power consumption problem. To implement stop-clock function, the paper analyzes some traditional clock control schemes. Based on them, the paper proposes one new clock control circuit which can be fully synthesized and tested. Compared with traditional clock control circuit, the scheme can provide more stable clock and be totally tested in DFT when reducing the chip power consumption.