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高密度封装进展之三——SiP与SoC 被引量:2

SiP vs SoC
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摘要 哪种方式更能提高LST的附加值?是SiP(system in a package)还是SoC(system on a chip)?LSI厂家正对此进行激烈争论。作为系统集成的选择方式,LSI厂家一直集中力量致力于SoC的开发。但是LSI厂家发现,仅靠SoC这一条路线已不能满足用户的要求。目前,对于各大LSI厂家来说,要不要转换其发展资源的投入方向,需要当机立断。 Which will be stronger for enbancing the added value of LSIs, SiP(system in a package)or SoC(system on a chip)?LSI makers are in the middle of this hot argument this is because both approaches have become rivals for the one choice of system integration technology, Up until now,LSI makers have been giving first priority to SoC development but makers have found it impossible to meet users' demands by only depending on SoC technology. On the other hand, the SiP technology has emerged rapidly in place of SoC as a means for realizing single-package integration. Every LSI maker is going to be forced to decide to change the way in which it invests its development resources.
作者 田民波
出处 《印制电路信息》 2003年第12期3-13,共11页 Printed Circuit Information
关键词 高密度封装 SIP SOC 系统集成 封装内系统 系统封装 HIC MCM LSI MCP 电子封装 印制电路 SiP(system in a package) SoC(system on a chip) IP(intellectual property) MCP(multi chip package)
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  • 1况延香,朱颂春.微电子封装的新进展领域及对SMT的新挑战[J].电子工艺技术,2004,25(5):225-229. 被引量:5
  • 2田民波.高密度封装进展之一 元件全部埋入基板内部的系统集成封装(下)[J].印制电路信息,2003,11(10):3-6. 被引量:3
  • 3蔡坚,王水弟,贾松良.系统级封装(SiP)集成技术的发展与挑战[J].中国集成电路,2006,15(9):60-63. 被引量:7
  • 4郑大安.以板级为基础的立体组装技术[C]∥成都:四川省电子学会生产技术专委会先进制造技术成果交流会论文集,2005:41-45.
  • 5RAHMAN A,REIF R. System Level Performance Evalua- tion of Threedimensional Integrated Circuits [ J ]. IEEE Trans,Very Large Scale Integr. (VLSI) Syst. , 2000,8 (6) :671 -678.
  • 6CHENG C H ,ERGUN A S,KHURI-YAKUB B T. Electri- cal Throughwafer Interconnects with Sub-pico Farad Para- sitic Capacitance [ C ] //Proc. Microelectromech. Syst. Conf. ,2001:18 -21.
  • 7LEUNG L L W, CHEN K J. Microwave Characterization and Modeling of High Aspect Ratio Through-wafer Inter- connect vias in Silicon Substrates [ J ]. IEEE Trans. Mi- crow. Theory Tech. ,2005,53(8) :2 472 -2 480.
  • 8CHOW E M,CHANDRASEKARAN V, PARTRIDGE A, et al. Process Compatible Polysilicon-based Electrical through Wafer Interconnects in Silicon Substrates [ J ]. J. Microelectromech. Syst. ,2002,11 ( 6 ) :631 - 640.
  • 9BURNS J A. A Wafer-scale 3-D Circuit Integration Tech- nology[J]. IEEE Trans. Electron Dev. ,2006,53(10): 2 507 -2 516.
  • 10PARK K T. A 45 nm 4 Gb 3-dimensional Double-stacked Multi-level NAND Flash Memory with Shared Bitline Structure[ C ] //IEEE ISSCC Dig. Tech. Papers, 2008 : 510 -511.

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