摘要
本文讨论了时钟信号的普遍描述和含时钟信号的触发器次态方程,并在此基础上提出了同步和异步时序电路的统一设计和分析理论。该理论的有效性已由实例予以证明。
The paper discusses general expresses of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, the unified theory for designing and analysing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.
基金
浙江省自然科学基金
关键词
时序电路
时钟信号
同步
异步
Sequential circuit, Clock signal, Logic design
