一种新型的FFT地址发生器集成电路的设计

Design of a New Type of FFT Address Generator IC

本文通过对ＦＦＴ计算流图的分析，得到了ＦＦＴ计算过程中连续参加蝶形运算的结点数据和三角常数ＷＮＫ的地址产生规律，并总结出逻辑表达式．在此基础上设计了一种新型的ＦＦＴ地址发生器．与传统设计方法相比，减少了晶体管数量，提高了速度，经逻辑模拟验证了设计上的正确性．由电路模拟可知，采用２μＣＭＯＳ工艺制作时，可达到５０ＭＨＺ的工作频率．

Through the study of FFT signal flow graph the rules were found in the binary addresses of the data and triangle factors(WNK) while calculating FFT,and the boolean expressions were synthesized.Therefore,a new type of FFT address generator was devised. Compared with the traditional ones,it has advantages of smaller number of transistors and higher speed. The design was verified through logical simulation. By using SPICE it was proved that this circuit is able to work at 50MHz fabricated by Zμm CMOS technology.