摘要
本文提出了一种处理信息量较大的双进位五输入加法器模块。通过九输入加法器及三数相加的串行进位加法器等设计实例证明了它能减少在运算电路中加法器模块的使用数量。
The paper proposes a five-input adder module with dual carry-out ,which can process more information. As examples,a nine-input adder and a serial carry-propagation adder for three multi-bit numbers are designed.It is shown that the number of adder module can be reduced in the design of arithmetic operation circuits with the module.
出处
《电子学报》
EI
CAS
CSCD
北大核心
1994年第11期84-86,共3页
Acta Electronica Sinica
基金
国家自然科学基金