Panda－Map：真值表结构FPGA的性能驱动的逻辑映射优化算法

Panda-Map:The Optimal Performance-Directed Logic Mapping Algorithm for TLU-Based FPGA

基于真值表ＴＬＵ（ＴａｂｌｅｏｆＬｏｏｋ－Ｕｐ）结构的ＦＰＧＡ（ＦｉｅｌｄＰｒｏｇｒａｍｍａｂｌｅＧａｔｅＡｒｒａｙ）在各种ＦＰＧＡ结构中占有越来越重要的地位。但迄今为止各种针对ＴＬＵＦＰＧＡ的逻辑映射算法都无法实现对面积和延迟的折衷考虑：不是只考虑面积优化，就是只考虑延迟优化，本文提出并实现了进行面积和延迟折衷的性能驱动的逻辑映射优化算法：Ｐａｎｄａ－Ｍａｐ，它是对面积驱动的Ｃｈｏｒｔｌｅ－ｃｒｆ［７］及延迟驱动的Ｃｈｏｒｔｌｅ－ｄ［６］的较大改进，并且Ｐａｎｄａ－Ｍａｐ采用了一种新的启发性算法将组合网络分割成若干个单输出子网络。

With TLU-based FPGA becoming more and more popular,various specific logic mapping algorithms have emerged for either area optimization or delay optimization. But until now there is no good logic mapping solution for the trade-off between area consideration and delay consideration. In this paper,we present an improved algorithm for above problem,which also adopts a novel heuristic algorithm to partition the DAG into single-output sub-DAGs.