VLSI栅阵列单元生成系成

VLSI Gate Matrix Cell Generation System

本文介绍一个新的ＶＬＳＩＣＭＯＳ电路栅阵列布图系统ＧＭＳ（ＧａｔｅＭａｔｒｉｘｌａｙｏｕｔＳｙｓｔｅｍ），它可以作为单元生成器在ＶＬＳＩ布图中自动产生基本单元。ＧＭＳ的布图过程包括：栅排序、线网分配和版图压缩，在考虑了许多实际约束条件的基础上，ＧＭＳ使用了一个新的栅排序算法，对Ｌｉ［６］算法做了较大改进，ＧＭＳ还把线网分配问题，转化为扩展的一维分配问题，在给出扩展一维分配问题定义的基础上，开发了一个线网分配算法，取得了较好的结果，ＧＭＳ允许用户对布图结果作叠代改进，对布图结果进行了压缩，从而减小了布图面积，ＧＭＳ已在ＭｉｃｒｏＶａｘＩＩ上用Ｃ语言实现，我们测试了许多实例，取得了较好的结果。

The paper presents a new gate matrix layout system:GMS for VLSI CMOS circuits.GMS can be used as a cell generator to produce basic cells automatically.The whole layout procedures in GMS are divided into gate assignment ,net assignment and compaction. Based on the consideration of many practical constraints,GMS uses a new gate assignment algorithm which can improve Li's algorithm[6] a lot.GMS also transfers net assignment into an extended l-dimensional assignment problem,and a heuristic algorithm is developed. GMS allows users to do interactive improvement on the layout results.It compacts the layout results to further reduce the used area.GMS has been implemented in C language on Micro VaxII.Many practical examples are tested and the experimental results are promising.