关于乘法器自检特性的研究

Study on Self-checking Multiplier

在建立采用余３码的自检并行乘法器结构后，完成乘法器检测分支的设计并全面讨论乘法运算分支的自检特性，给出全加器等各子电路的自检设计要求。

After setting up the structure of self-checking parallel multiplier with residue 3 code, design of multiplier test branch is finished. Then, the self-checking attribute of multiplication branch is discussed in every aspects.The demands of self-checking design on subcircuits such as full adder are given.