VLSI综合的逻辑最小化算法

Logic Minimization Algorthms for VLSI Synthesis

本文讨论了逻辑函数的多维体空间表示方法和运算方法，探讨了接近最小覆盖的两级与－或网络的自动逻辑综合方法．提出不经过求出全部质蕴涵项而直接构成函数的无冗余覆盖的算法。

The geometrical representation by Boolean n-cubes and the operation for logic functionsare discussed.The automatic logic synthesis of two-level AND-OR network for near mini-mum cover is investigated.A new aigorithm of generating a function with irredundant coverbut without the necessity of finding all the prime implicants is proposed.The algorithm ismainly used in the automatic synthesis of the programmable logic array(PLA)and the AND-OR network.