串行反馈内置自测试设计的研究

SERIAL FEEDBACK BUILT-IN SELF-TEST SCHEME

本文给出一种串行反馈内置自测试设计结构，分析了它的状态转移图的拓扑结构，并对若干电路做了模拟实验。研究表明：添加反馈线沟通测试图形生成和响应压缩部分，既能提高测试图形的随机性，又可以降低错误特征被漏检的可能性，从而提高故障覆盖率。

A serial feedback- based scheme for built-in at-speed self-test is proposed in this paper. By using on-chip feedback lines to link PRPG and MISR, aliasing can be reduced, compared to a conventional output register MISR. The analysis of State Transition Graph (STG) topology reveals that it is possible to design a serial feedback-based BIST structure yielding STGs of disjunct rings only. If a large ring is found, it will be a candidate for a test sequence leading to a high fault coverage.