摘要
本文讨论脉动芯片A110的若干级联形式,分析推导级联中A110的延迟寄存器参数,给出确定这些参数的规则。由于采用卷积运算的显式表达式并加以脉动处理的约束条件,所以推导过程在概念上清楚,易于理解。
This paper discusses several ways of cascading A110s for more powerful systolic convolution arrays, and gives general rules for determining tbe parameters of the programmable shift registers (PSRs). Because explicit expressions of convolution and constraint for systolic processing are used for analysis, tbe derivation process is conceptually clear and therefore easy to unederstand.
出处
《模式识别与人工智能》
EI
CSCD
北大核心
1994年第3期248-253,共6页
Pattern Recognition and Artificial Intelligence
关键词
脉动芯片
延迟寄存器
参数
卷积
Signal Processing, Image Processing, Systolic Array, Convolutioa, Cascade.