一种新的多总线多处理机系统互连网结构

A New Interconnection Network Architecture for Multiple Bus Multiproces-sor Systems.

该文提出了一个新的多处理机互逆网结构，称之谓层次型多总线多处理机系统结构。该结构适合子中大规模的多处理机系统。同时分析了它的有效存贮器带宽性能，获得的模型基于访存请求均匀分布于各存贮器模块。

This paper presents a new architecture for multiproces-sor systems,called hierarchical multiple bus multiprocessor,which is applied for the medium and large size of multiprocessor systems.The effective memory bandwidth performance of this system is analyzed under the assumption that the memory requests are uniformly distributed among the memory modules.