可编程逻辑阵列嵌入自测试设计

Built-in Self Test Design for PLA

本文提出的设计方案,以极低的附加硬件资源覆盖了包括附加电路在内的所有单重固定故障、交叉点故障、邻线桥接故障和几乎所有的多重故障。同现今通行的设计方案相比,具有下列明显优点:1) 极低的附加硬件资源;2) 极高的故障被测度;3) 对可编程逻辑阵列的正常操作没有影响;4) 减少了测试延迟;5) 故障检测异常简单。

Built-in self test design scheme for PLA proposed in this paper covers single and multiple stuck-at fault, crosspoint faults as well as adjacent lines bridging faults, including those faults in addtional circuits, with much lower extra hardware overhead. Compared with existed schemes, the salient advantages are: 1) Much lower additional hardware overhead. 2) Much higher fault coverage. 3) No impact on mormal operation of PLA. 4) Rcducing per test delay. 5) Extraordinarily simple fault detection.