摘要
提出了一种利用计算机检验组合逻辑电路中的竞争冒险的理论和方法。
The paper describes the underlying theory and a method which is designed to utilize the computer to detect and locate tile presence of logic hazards in combinatorial logic circuit.
关键词
组合逻辑电路
计算机
矩阵代数
冒险
Combinatorial logic circuits, Computer, Matrix algebra, Hazards
