一种极大似然估计的自动变阶位同步方案

A MLE-based Bit Synchronization Scheme with Automatic Order Changing

本文针对时分多址数字传输系统提出了一种新的位同步方案。该方案在数字锁相环中加入自动变阶电路，并采用极大似然估计（ＭＬＥ）结构，以同时满足同步速度与精度两方面的要求。文中给出了方案的框图、工作原理及性能分析。

in this paper, a new bit synchronization scheme for TDMA digital transmission system it proposed. In the scheme, digital phase-locked loop(DPLL) is supplemented by an automatic order-changing circuit, together with a Maximum Likelihood Estimetion structure (MLE) in order tc meet both requirements of synchronization speed and precision. In the paper, block diagram, operation principle and performance analysis of the new scheme are given.