60路32kb／s　ADPCM转换器的大规模集成电路设计

VLSI Design for 60-channel 32kb/s ADPCM Convertor

３２ｋｂ／ｓＡＤＰＣＭ转换设备的研制在数字通信领域具有显著的社会与经济效益。本文的工作是在用中小规模集成块构成了６０路转换编译码系统样机的基础上，进行了大规模专用集成电路（ＡＳＩＣ）芯片的电路设计，拟用两片５０００门门阵列实现全系统集成。目前，线路级的设计已经完成，并且成功地通过了Ｄａｉｓｙ工作站的计算机逻辑模拟。

The development of 32kb/s ADPCM convertor equipment is of social and economic benefit in digital communication area.Our work is based on a 60-channel codec sample machine composed of middle scale IC and small scale IC having been structured. We conducted the circuit design for large scale application specific IC chip.The whole-system-ASIC-chip integrated in two 5000 gate gate array is being expected.The design, now, has passed the logic simulation successfully in Daisy computer workstation.