RS-PC译码器芯片设计的FPGA验证

FPGA Verification of the Design of RS-PC Decoder Chip

在分析FPGA验证对ASIC设计的作用的基础上 ,提出了一种为了验证RS -PC译码器芯片设计的FPGA验证方案。该方案具有可测试性强 ,灵活和通用的特点。

Based on the anaysis of function of FPGA verification for ASIC design, a FPGA verification method for a RS-PC decoder chip is presented. The method features good testability and smart and general purpose.